1. Field of the Invention
Embodiments of the present invention relate to semiconductor fabrication, and in particular, to patterning of narrow device features such as gate lines.
2. Background Technology
The emphasis on increased semiconductor device performance has led to investigation of ways to increase device speed. One way of increasing device speed is to reduce the size of individual circuit components and the wiring that connects them. This enables circuit components to operate faster and to be placed closer together, and enables more circuit components to be used in a given device.
The reduction of MOSFET gate line width is particularly important since this dimension is closely tied to switching speed and operating voltage. However, MOSFET gate lines patterned using only traditional projection lithography techniques are limited by the minimum feature size that can be patterned in a photoresist mask. Accordingly, supplemental techniques for further reducing gate line widths have been developed One such technique involves oxidizing the gate line sidewalls to reduce gate line width. FIGS. 1a-1c show structures formed during such processing. As shown in FIG. 1a, a polysilicon gate line 14 is formed on a silicon oxide gate insulating layer 12 that overlies a semiconductor substrate 10. The polysilicon gate line is patterned using a hardmask 16. FIG. 1b shows the structure of FIG. 1 a after the structure has been reacted in an oxidizing atmosphere such as an oxygen plasma to create oxidized sidewall portions 18 on the gate line 14. FIG. 1c shows the structure of FIG. 1b after stripping of the hardmask and the oxidized sidewall portions. The resulting polysilicon gate line 14 is significantly narrower after this processing. However, as seen in FIG. 1b, the oxidizing atmosphere has a pronounced effect at the corners of the polysilicon gate line near their junction with the underlying gate oxide layer 12. This effect is produced by the diffusion of oxygen through the oxide layer 12 toward the polysilicon gate line 14. The result is an undercutting oxide growth 20 around the edges of the gate line 14 at its junction with the underlying gate insulating layer 12. The undercutting portion 20 of the oxide remains in the final gate structure as seen in FIG. 1c, resulting in degraded short channel control and thus degraded device performance.
Consequently, there is a need for further techniques for providing further narrowing of semiconductor device dimensions and reductions in gate widths.
It is an object of the present invention to provide a method and apparatus for defining narrow semiconductor device geometries. It is a further object of the present invention to provide a method for reducing the width of MOSFET gate lines.
In accordance with one embodiment of the invention, patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and at least a portion of the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the gate line from undercutting growth of reacted material.
In accordance with another embodiment of the invention, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line.